Optical packet switches and routers process packets in an optical domain. Optically switching packets presents challenges that may not exist in electronic packet switching equipment. For example, packets can arrive asynchronously on various input links on the packet switching device. In an electronic router, the data is synchronized relatively easily link interface. For example, the asynchronously arriving packets can be stored in a First In-First Out (FIFO) buffer while waiting for subsequent packet processing. Packets are written into the FIFO when they arrive and are read only when the downstream packet processing stage is ready.
However, in optical switching architectures there are no equivalent elastic buffering devices. Thus, problems can arise when one or more asynchronous packet streams converge at some synchronous processing point (a.k.a., convergence point). In one example, the convergence point could be, but is not limited to, a synchronous switch fabric. The switch fabric, regardless of the existence of Virtual Output Queues (VOQs), may include optical input buffers preceding different synchronization convergence points. Other convergence points can include optical output buffers or output interfaces without buffers that may be connected to an asynchronous switch fabric (e.g., a mesh). Unfortunately, optical buffers are typically synchronous devices in that the time difference between when data enters and leaves is a multiple of a fixed delay.
Various optical buffer architectures have been proposed in the past, and some have been implemented for testing. There are two basic methods currently used to avoid packet contention at a convergence point. One technique uses some type of delay and the second technique uses some type of avoidance. The avoidance schemes, as the name suggests, avoid the contention problem but only work to a limited scale.
The delay schemes use an optical packet “aligner” circuit on each path to the convergence point. The packet aligners simply delay the incoming signal on each path by a preconfigured constant amount. Unfortunately, it is difficult to control the aligner circuits for each packet on each path. Further, these delay schemes do not take into account asynchronously arriving packets and therefore do not have the capacity to synchronize these asynchronous packets with a synchronous optical convergence point.
The present invention addresses these and other problems associated with the prior art.